1. Field of the Invention
The present invention relates a drive circuit for driving a power device such as an IGBT or a MOSFET and, more particularly, to a power device drive circuit capable of preventing transmission of an erroneous signal due to negative noise or dv/dt in a high-potential-side reference potential.
2. Background Art
FIG. 11 is a diagram showing a conventional power device drive circuit. This drive circuit includes a level shift circuit 10, a transmission circuit 11 and a driver circuit 12. The level shift circuit 10 has resistors R1 and R2 and high-withstand-voltage NMOS transistors T1 and T2. The transmission circuit 11 has an RS flip-flop 16 and a mask circuit 17. The mask circuit 17 has, as shown in FIG. 2, inverter gates 18 and 19, NAND gates 20 and 21, NOR gates 22 and 23, and an AND gate 24.
An ON signal and an OFF signal for controlling the on/off operations of a power device are input to the level shift circuit 10. The ON and OFF signals are signals in pulse form, which are output from a low-potential-side control circuit 32 and input to the high-withstand-voltage NMOS transistors T1 and T2 of the level shift circuit 10 to be level-shifted to a high potential. The level-shifted ON and OFF signals are transmitted to the power device (not shown) through the transmission circuit 11 and the driver circuit 12.
In ordinary cases, the load on a power device driven by a drive circuit is an inductance load such as a motor and a fluorescent lamp. There is a possibility of the potential of a ground 33 of the drive circuit (high-potential-side reference potential) being changed to the negative side with respect to the potential of a ground 14 at the time of switching due to negative noise or dv/dt in the high-potential-side reference potential under the influence of the inductance load and a parasitic inductance component due to wiring on the printed circuit board.
In such a case, currents flow through the resistors R1 and R2 connected to the ground 33 due to parasitic capacitances and parasitic diodes or the like of the high-withstand-voltage NMOS transistors T1 and T2 to cause voltage drops. The ON and OFF signals are thereby reduced abruptly to cause an erroneous signal, which is transmitted to cause the power device to malfunction.
In order to prevent this malfunction, the mask circuit 17 is provided. The mask circuit 17 stops transmission of the ON and OFF signals to the RS flip-flop 16 when both the ON and OFF signals are lower than a first threshold level (see, for example, Japanese Patent Laid-Open 2003-273715).
A situation where the outputs from the level shift circuit 10, i.e., the ON and OFF signals, are abruptly lowered due to the influence of dv/dt for example, as shown in (a) of FIG. 12, will be considered. In (a) of FIG. 12, the threshold level (first threshold level) of inverter gates 18 and 19 of the mask circuit 17 is indicated by broken line A. The output signals from the inverter gates 18 and 19 of the mask circuit 17 and the output signal from the AND gate 24 change as shown in (b) to (d), respectively, of FIG. 12.
If a potential difference occurs between the ON and OFF signals due to variation in the parasitic capacitances of the high-withstand-voltage NMOS transistors T1 and T2, the range in which the output signal from the AND gate is active (high) is narrower than the range in which the output signal from the inverter gate 18 or 19 is active (high). There is, therefore, a problem that an erroneous signal is transmitted from the NOR gate 22 on the On side to the RS flip-flop 16, as shown in (e) of FIG. 12.